The present invention relates to a semiconductor memory device, and more particularly to a random access memory device of a static type (called hereinafter as a "SRAM").
In a SRAM, each of memory cells is comprised of first and second IGFETs (insulated gate field effect transistors) and first and second loads. The first IGFET and first load are connected in series, and the second IGFET and second load are also connected in series. The connection point of the first IGFET and first load, i.e. a first node, and that of the second IGFET and second load, i.e. a second node, are connected to the gates of the second and first IGFETs, respectively. Each memory cell is disposed at each intersection of a plurality of word (row) lines and bit (column) lines. More specifically, first and second transfer gates are inserted between the first node and one of a pair of bit lines and between the second node and the other bit line, respectively, and these transfer gates are controlled by one word line. When the word line is selected in response to address signals, the first and second transfer gates are brought into an open state, so that the first and second nodes of each memory cell are electrically connected to a pair of the bit lines, respectively.
In a data-write operation wherein a write-enable signal and a data to be stored are supplied, a pair of bit lines are coupled to a data input circuit which in turn controls the relationship in potential between the bit lines in pair in response to the data to be stored. Either the first or second IGFET of the accessed memory cell is thereby turned on, and the conductive state of the first or second IGFET is maintained. On the other hand, in a data-read operation wherein the write-enable signal is not supplied, a pair of bit lines are coupled to a data output circuit. Since the potential difference is developed between the bit lines by the maintained conductive state of one of the first and second IGFET's and non-conductive state of the other IGFET in the accessed memory cell, the data output circuit detects the potential difference and produces an output data corresponding to the data stored in the accessed memory cell.
Thus, either one of the first and second IGFETs of each memory cell in the SRAM is always in the conductive state. For this reason, a d.c. current continues to flow into the first or second IGFET through one or the other of a pair of bit lines so long as the selected word line is energized. In addition, many memory cells are simultaneously accessed by the same word line. Accordingly, if the selected word line is energized during a whole period of each cycle of the data-write and data-read operations, a very large power current is dissipated.
One of the measures to reduce such power dissipation would be to shorten the energizing time of the selected word line during each cycle period of the data-write and data-read operations. For example, a clock generator may be provided to generate a one-shot pulse in response to the change in address signals and also generate it in response to the receipt of the write-enable signal, the generated one-shot pulse being used to energize the selected word line. Thus, the energizing time of the selected word line is shortened or limited to the time duration of the one-shot pulse and the d.c. current only flows during a limited period of time corresponding to the pulse width of the one-shot pulse.
This measure is not satisfactory, however, because the data to be written into the SRAM is often supplied to the SRAM after a relatively long period of time has elapsed from a point in time at which the write-enable signal is applied, that is, at the timing after the one-shot pulse disappears, such that the data would not be stored.